The present invention relates to a solid state image sensor comprising a plurality of pixels formed by static induction transistors having both photoelectric converting function and switching function.
Heretofore, there have been proposed various solid state image sensors comprising static induction transistors (hereinafter abbreviated as SIT). For instance, there has been proposed a solid state image sensor comprising normally-off type SITs which are in cut-off condition under the zero gate bias. In such a solid state image sensor comprising normally-off type SITs, since a signal is read out at a charge injection region, it is possible to obtain a spike-like signal having a large amplitude. However, an effective dynamic range of a gate potential during a readout period is limited to a relatively small range from a positive pinch-off voltage at which the SIT begins to conduct to a gate voltage at which the charge injection from a gate to a source occurs. Therefore, the effective dynamic range of incident light is small and the saturated exposure value is small.
In order avoid the drawback mentioned above, there has been proposed in U.S. patent application Ser. No. 647,169 filed on Sept. 4, 1984 a solid state image sensor comprising normally-on type SITs which are made conductive under the zero gate bias condition.
FIGS. 1A and 1B show an embodiment of the solid state image sensor comprising normally-on type SITs as proposed in the above mentioned Patent Application. A SIT 1 shown in FIG. 1A comprises an n.sup.+ or n substrate 2 which serves as a drain of the SIT, an n.sup.- epitaxial layer 3 which is grown on the substrate 2, and serves as a channel, an n.sup.+ source region 4 and a p.sup.+ gate region 5 formed in the epitaxial layer 3 by means of, for example, thermal diffusion, a source electrode 6 connected to the source region 4 and a gate electrode 8 arranged above the gate region 5 over an insulating film 7 such as SiO.sub.2 to form a gate capacitor 9. The SIT 1 is isolated from adjacent SITs by means of an isolation region 10 formed by a burried insulation substance. A number of SITs are arranged in a matrix on the same substrate.
FIG. 1B is a circuit diagram illustrating the whole construction of a solid state image sensor comprising SITs shown in FIG. 1A. To drains (substrate) of SITs 1-11 to 1-mn forming pixels arranged in a matrix are commonly applied a video voltage V.sub.D, and to gate electrodes of SITs 1-11 to 1-1n; . . . ; 1-m1 to 1-mm arranged in the X direction, i.e. in row are connected row lines 11-1 to 11-m, respectively which lines are then connected to a vertical scanning circuit 12 are applied row selection signals .phi..sub.G1 to .phi..sub.Gm. Source electrodes of SITs 1-11 to 1-m1; . . . ; 1-1n to 1-mn arranged in the Y direction, i.e. in column, are connected to column lines 13-1 to 13-n, respectively, having first ends connected to ground via respective column selection transistors 14-1 . . . 14-n, a common video line 15 and a load resistor 16. To gates of the column selection transistors 14-1 to 14-n are applied column selection signals .phi..sub.s1 to .phi..sub.sn, respectively, from a horizontal scanning circuit 17. The other ends of the column selection lines 13-1 to 13-n are connected to ground via respective reset transistors 18-1 . . . 18-n. A reset signal .phi..sub.R is commonly applied to the gates of reset transistors 18-1 . . . 18-n.
FIGS. 2A to 2G illustrate waveforms of the signals applied to the row lines 11-1 to 11-m, column selection transistors 14-1 to 14-n and reset transistors 18-1 to 18-n. As illustrated in FIGS. 2A to 2G, in this solid state image sensor, the successive pixels are readout by successively selecting the row lines 11-1 to 11-n as well as by successively selecting the column lines 13-1 to 13-n while a row line has been selected. During the horizontal blanking period t.sub.BL after signal readout period t.sub.H, all the SITs belonging to a respective row line are simultaneously reset. Since each pixel is formed by a normally-on type SITs, each of the row selection signals .phi..sub.G1 to .phi..sub.Gm has three levels so as to effect a readout at a negative pinch-off voltage V.sub..phi.G.
During the horizontal blanking period t.sub.BL, all the column lines 13-1 to 13-n are set to zero voltage by means of the reset signal .phi..sub.R applied simultaneously to the reset transistors 18-1 to 18n. At the same time, a row selection signal .phi..sub.G1 applied to a row line, for instance, a first row line 11-1, has the maximum voltage V.sub..phi.R, and therefore the floating gate of all the SITs 1-11 to 1-1n connected to the respective row line 11-1, i.e. a junction between the gate region and gate capacitor, is forward biased with respect to the source connected to the column lines 13-1 to 13-n having zero potential. Therefore, photocarriers (holes) induced by a light input and stored in the gate region flow into the source region and the potential of the floating gate with respect to the source becomes equal to a built-in voltage V.sub.bi between the gate and source. In this manner, the gates of SITs belonging to one row are reset and photocarriers stored in the gates are discharged.
In each row line, when the application of the voltage V.sub..phi.R ends, the gate region of the SIT belonging to the respective row is reverse biased substantially by -V.sub..phi.R with respect to the built-in voltage V.sub.bi. More accurately, the gate region is reverse biased by ##EQU1## where C.sub.G is a capacitance of the gate capacitor 9, and C.sub.J is a stray junction capacitance of the floating gate with respect to the source and channel. Therefore, the gate potential of the respective SIT becomes equal to ##EQU2##
During the signal readout period t.sub.H, since the voltage V.sub..phi.G is applied to a selected row line, the potential of the floating gates of SITs connected to the respective row line is increased substantially by V.sub..phi.G due to capacitive coupling. Until the time instant of signal readout, holes of electron-hole pairs induced by the incident light in the epitaxial layer have been stored in the gate region from a time instant when the respective row was reset last. Therefore, the floating gate potential is increased by .DELTA.V.sub.Gp =Q.sub.p /C.sub.G, wherein Q.sub.p is an integrated amount of holes. Thus, the gate potential at the time of readout becomes substantially equal to (V.sub.bi -V.sub..phi.R)+V.sub..phi.G +Q.sub.p /C.sub.G. Now it is assumed that the pinch-off voltage V.sub.GO of respective SIT is set to (V.sub.bi -V.sub..phi.R +V.sub..phi.G). Then, the amount of the gate potential exceeding the pinch-off voltage V.sub.GO becomes equal to the potential increment .DELTA.V.sub.GP due to the integration of the induced photocarriers for an image pick-up period. In this manner, it is possible to obtain a relative output voltage V.sub.out in proportion to a relative light input P as shown in FIG. 3A, and a single current I.sub.D flows in proportion to the gate potential V.sub.G as illustrated in FIG. 3B.
In the above explained solid state image sensor, after the reset of the gate potential, but before the signal readout, when a strong light is incident, the increment .DELTA.V.sub.Gp of gate potential due to the accumulation of a large amount of photocarriers might exceed V.sub..phi.G. Then, the floating gate potential V.sub.G becomes as follows. EQU V.sub.G =V.sub.bi -V.sub..phi.R +.DELTA.V.sub.Gp &gt;V.sub.GO
Therefore, even if the SIT is not selected, the gate potential V.sub.G might exceed the pinch-off voltage V.sub.GO and thus, the SIT is errorneously made conductive. Then, a current readout from the non-selected SIT which is errorneously made conductive is superimposed upon a signal current readout from a correctly selected SIT and flows through the load resistor 16. In this manner, it is no longer possible to effect image pick-up operation accurately.
In order to avoid the above drawback, the inventor has considered that the maximum allowable increment .DELTA.V.sub.Gp of gate potential is made higher by increasing the row selection voltage V.sub..phi.G and reset voltage V.sub..phi.R, while the pinch-off voltage V.sub.GO remains unchanged. However, this means that the saturation light exposure value is changed and thus, freedom of designing the solid state image sensor is limited. Moreover, since said allowable increment can not be made sufficiently high, if much stronger light is made incident upon the solid state image sensor, the above drawback might still occur. Therefore, the above explained measure can not provide a fundamental solution for the above problem.
As explained above, in the solid state image sensor comprising normally-on type SITs, although it is possible to obtain a wider effective range of SIT gate potential and thus a wider range of incident light and a larger saturation light exposure amount as compared with a solid image sensor having normally-off type SITs, the gate potential V.sub.G might exceed the pinch-off voltage V.sub.GO when a large amount of light is made incident and errorneous signal current might be readout from one or more SITs which are not fully selected, but are half selected. This is sometimes called the half selection signal phenomenon.